Low-Power Control Register (Lpwrcr) - Renesas H8S/2633 Series Hardware Manual

Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and sub-active mode * .
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode * .
Note: * This function is not available in the H8S/2695.
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0
0 0 0
1
1 0
1
1 0 0
1
1 —
24.2.3

Low-Power Control Register (LPWRCR)

H8S/2633 Series, H8S/2633R
Bit :
DTON
Initial value :
R/W
R/W :
H8S/2695
Bit :
— *
Initial value :
R/W :
Note: * On the H8S/2695 only 0 should be written to these bits.
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a power-on reset and when in hardware standby mode. It is
not initialized at a manual reset or when in software standby mode. The following describes bits 7
to 2. For details of other bits, see section 23A.2.2 and 23B.2.2, Low-Power Control Register
(LPWRCR).
992
Description
Bus master in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
7 6 5
LSON NESEL
0 0 0
R/W R/W
7 6 5
— * — *
0
0 0
R R R/W
4 3
SUBSTP RFCUT
0 0
R/W R/W
4 3
— * — *
0 0
R/W R/W
(Initial value)
2 1
— STC1 STC0
0 0
R/W R/W R/W
2 1
— STC1 STC0
0 0
R/W R/W R/W
0
0
0
0