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Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS
Description
0
Specified multiplication factor is valid after transition to software standby mode,
watch mode, and subactive mode
1
Specified multiplication factor is valid immediately after STC bits are rewritten
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master
clock.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
0
0
0
1
1
0
1
1
0
0
1
1
—
23B.2.2 Low-Power Control Register (LPWRCR)
H8S/2633R
Bit
:
7
DTON
Initial value :
0
R/W
:
R/W
H8S/2695
Bit
:
7
—*
Initial value :
0
R
R/W
:
Note: * On the H8S/2695 only 0 should be written to these bits.
Description
Bus master is in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
6
5
LSON
NESEL
SUBSTP
0
0
R/W
R/W
R/W
6
5
—*
—*
—*
0
0
R
R/W
R/W
4
3
2
RFCUT
—
0
0
0
R/W
R/W
4
3
2
—*
—
0
0
0
R/W
R/W
(Initial value)
(Initial value)
1
0
STC1
STC0
0
0
R/W
R/W
1
0
STC1
STC0
0
0
R/W
R/W
973
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