System Clock Control Register (Sckcr) - Renesas H8S/2633 Series Hardware Manual

24.2.2

System Clock Control Register (SCKCR)

Bit : 7
PSTOP
Initial value : 0
R/W : R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): In combination with the DDR of the applicable port,
this bit controls ø output. See section 24.12, ø Clock Output Disabling Function, for details.
High-Speed Mode,
Bit 7
Medium-Speed Mode,
Sub-Active Mode *
PSTOP
0 ø output (initial value)
1 Fixed high
Note: * This function is not available in the H8S/2695.
Bits 6 to 4—Reserved: These bits are always read as 0 and cannot be modified.
Bit 3—Frequency Multiplication Factor Switching Mode Select (STCS): Selects the operation
when the PLL circuit frequency multiplication factor is changed.
Bit 3
STCS Description
0 Specified multiplication factor is valid after transition to software standby mode, watch
mode * , or subactive mode *
1 Specified multiplication factor is valid immediately after STC bits are rewritten
Note: * This function is not available in the H8S/2695.
6 5 4
— — —
0 0 0
— — —
Description
Sleep Mode,
Sub-Sleep Mode *
ø output
Fixed high
3 2
STCS SCK2
0 0
R/W R/W
Software Standby
Mode, Watch Mode * ,
Direct Transition
Fixed high
Fixed high
1 0
SCK1 SCK0
0 0
R/W R/W
Hardware Standby
Mode
High impedance
High impedance
(Initial value)
991