Bus Master Clock Selection Circuit; Subclock Oscillator (This Function Is Not Available In The H8S/2695) - Renesas H8S/2633 Series Hardware Manual

23B.6 Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed
clocks (ø/2, ø/4, ø/8, ø/16, and ø/32) to be supplied to the bus master, according to the settings of
the SCK2 to SCK0 bits in SCKCR.
23B.7 Subclock Oscillator (This function is not available in the H8S/2695)
(1) Connecting 32.768kHz Quartz Resonator
To supply a clock to the subclock oscillator, connect a 32.768kHz quartz resonator, as shown in
figure 23B-8. See section 23B.3.1, Notes on Board Design for notes on connecting crystal
resonators.
Figure 23B-8 Example Connection of 32.768kHz Crystal Resonator
Figure 23B-9 shows the equivalence circuit for a 32.768kHz resonator.
OSC1
Figure 23B-9 Equivalence Circuit for 32.768kHz Resonator
980
OSC1
OSC2
L C
s s
C
1
C
2
C =C
1
R
s
C
o
=15pF (typ)
2
OSC2
C =1.5pF (typ.)
o
R =14kΩ (typ.)
s
f =32.768kHz
w