Section 23B Clock Pulse Generator (H8S/2633R, H8S/2695); Overview; 1.1 Block Diagram - Renesas H8S/2633 Series Hardware Manual

Section 23B Clock Pulse Generator
23B.1 Overview
The H8S/2633R has a built-in clock pulse generator (CPG) that generates the system clock (ø), the
bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator, PLL (phase-locked loop) circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock
oscillator, and waveform shaping circuit. The frequency can be changed by means of the PLL
circuit in the CPG. Frequency changes are performed by software by means of settings in the
system clock control register (SCKCR) and low-power control register (LPWRCR).
The input clock frequency is 2 MHz to 25 MHz. With the H8S/2633R and H8S/2695 PLL must be
set to use a multiplier of × 2 or × 4 when operating at frequencies of 25 MHz < ø ≤ 28 MHz.
23B.1.1 Block Diagram
Figure 23B-1 shows a block diagram of the clock pulse generator.
EXTAL
System
clock
oscillator
XTAL
1
*
OSC1
Subclock
oscillator
OSC2
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
Note: *1 This function is not available in the H8S/2695.
*2 The input clock frequency is 2 MHz to 25 MHz. With the H8S/2633R and H8S/2695 PLL must be set to use
a multiplier of × 2 or × 4 when operating at frequencies of 25 MHz < ø ≤ 28 MHz.
Figure 23B-1 Block Diagram of Clock Pulse Generator
(H8S/2633R, H8S/2695)
LPWRCR
STC1, STC0
*2
PLL circuit
(×1, ×2, ×4)
Clock
selection
circuit
ø SUB
Waveform
shaping
circuit
WDT1
count
clock
Medium-
speed
ø/2 to
clock divider
ø/32
ø
System clock Internal clock to
to ø pin supporting modules
SCKCR
SCK2 to SCK0
Bus
master
clock
selection
circuit
Bus master clock
*1
to CPU, DMAC
*1
and DTC
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