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WDT1
TCSR
Bit 4
1
PSS *
Description
•
0
TCNT counts the divided clock from the ø -based prescaler (PSM).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode.
•
1
TCNT counts the divided clock from the øsubclock-based prescaler (PSS).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode *
•
When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode, watch mode, or high-speed mode.
Notes: *1 In the H8S/2695 only a 0 may be written to the PSS bit in the TCSR1 register.
*2 Always set high-speed mode when shifting to watch mode or sub-active mode.
24.2.5
Module Stop Control Register (MSTPCR)
MSTPCRA
Bit
:
7
MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
Initial value :
0
R/W
:
R/W
MSTPCRB
Bit
:
7
MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
Initial value :
1
R/W
:
R/W
MSTPCRC
Bit
:
7
MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
Initial value :
1
R/W
:
R/W
MSTPCR, comprising three 8-bit readable/writable registers, performs module stop mode control.
996
6
5
0
1
R/W
R/W
R/W
6
5
1
1
R/W
R/W
R/W
6
5
1
1
R/W
R/W
R/W
2
, or sub-active mode *
4
3
2
1
1
1
R/W
R/W
4
3
2
1
1
1
R/W
R/W
4
3
2
1
1
1
R/W
R/W
(Initial value)
2
.
1
0
1
1
R/W
R/W
1
0
1
1
R/W
R/W
1
0
1
1
R/W
R/W
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