Section 3 Exception Handling; Overview; Reset; Reset Sequence - Renesas F-ZTAT H8 Series Hardware Manual

3.1

Overview

Exception handling is performed in the H8/3857 Group when a reset or interrupt occurs. Table 3.1
shows the priorities of these two types of exception handling.
Table 3.1 Exception Handling Types and Priorities
Priority Exception Source
High

Reset

Interrupt
Low
3.2 Reset
3.2.1 Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2

Reset Sequence

As soon as the RES pin goes low, all processing is stopped and the H8/3857 enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
When the RES pin goes high again after being held low for a given period, reset exception
handling begins. Reset exception handling takes place as follows:
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
When system power is turned on or off, the RES pin should be held low.

Section 3 Exception Handling

Time of Start of Exception Handling
Exception handling starts as soon as the reset state is cleared
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling
in progress is completed
3. Exception Handling
Rev.3.00 Jul. 19, 2007 page 71 of 532
REJ09B0397-0300