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20.4.4
Sample Application of Software Standby Mode
Figure 20.1 shows an example in which software standby mode is entered at the fall of NMI and
exited at the rise of NMI.
With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an
NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit
is set to 1; then the SLEEP instruction is executed to enter software standby mode.
Software standby mode is exited at the next rising edge of the NMI signal.
Clock
oscillator
φ
NMI
NMIEG
SSBY
Figure 20.1 NMI Timing for Software Standby Mode (Example)
20.4.5
Note
The I/O ports retain their existing states in software standby mode. If a port is in the high output
state, its output current is not reduced.
NMI interrupt
Software standby
handler
mode (power-
NMIEG = 1
down state)
SSBY = 1
SLEEP
instruction
Section 20 Power-Down State
Oscillator
NMI exception
settling time
handling
(t
)
osc2
Rev. 3.00 Mar 21, 2006 page 627 of 814
REJ09B0302-0300
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