Renesas F-ZTAT H8 Series Hardware Manual page 418

Section 10 16-Bit Integrated Timer Unit (ITU)
Contention between Buffer Register Write and Input Capture: If a buffer register is used for
input capture buffering and an input capture signal occurs in the T
capture takes priority and the write to the buffer register is not performed. See figure 10.69.
φ
Address bus
Internal write signal
Input capture signal
GR
BR
Figure 10.69 Contention between Buffer Register Write and Input Capture
Rev. 3.00 Mar 21, 2006 page 390 of 814
REJ09B0302-0300
Buffer register write cycle
T T
1 2
BR address
N
M
state of a write cycle, input
3
T
3
X
TCNT value
N