Register Configuration; System Control Register (Syscr) - Renesas F-ZTAT H8 Series Hardware Manual

17.1.2

Register Configuration

The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
Address *
Name
H'FFF2 System control register
Note: * Lower 16 bits of the address.
17.2

System Control Register (SYSCR)

Bit 7
SSBY
Initial value 0
Read/Write R/W
Software standby
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
6 5
STS2 STS1 STS0
0 0
R/W R/W R/W
Standby timer select 2 to 0
Abbreviation
SYSCR
4 3 2
UE NMIEG
0 1 0
R/W R/W
NMI edge select
User bit enable
Rev. 3.00 Mar 21, 2006 page 553 of 814
Section 17 RAM
R/W Initial Value
R/W H'0B
1 0
— RAME
1 1
— R/W
RAM enable
Enables or
disables
on-chip RAM
Reserved bit
REJ09B0302-0300