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ForgeFPGA Configuration Guide
This document describes how to configure the ForgeFPGA core from three different configuration bitstream
sources: External SPI/QSPI Flash, Internal OTP, MCU as a host.
Contents
1.
Terms and Definitions ................................................................................................................................... 1
2.
References ...................................................................................................................................................... 1
3.
Introduction .................................................................................................................................................... 2
4.
General SPI Interface ..................................................................................................................................... 2
4.1
SPI Modes with Clock Polarity and Clock Phase .................................................................................. 3
5.
Development Board ....................................................................................................................................... 4
6.
OTP Read/Write .............................................................................................................................................. 7
6.1
Writing the OTP Block ........................................................................................................................... 9
6.2
Reading the OTP Block ....................................................................................................................... 10
6.3
Read Command Structure ................................................................................................................... 11
7.
QSPI Programming (Master Mode) ............................................................................................................ 11
8.
MCU Programming (Slave Mode) ............................................................................................................... 13
Conclusion ........................................................................................................................................................... 14
9.
Revision History .......................................................................................................................................... 15
1. Terms and Definitions
OTP
One Time Programmable on chip NVM
QSPI
Quad Serial Programming Interface
MCU
Micro Controller Unit
FPGA
Field-Programmable Gate Array
CPOL
Clock Polarity
CPHA
Clock Phase
2. References
[1]
SLG47910, Datasheet, Renesas Electronics Corporation
[2]
ForgeFPGA Designer
[3]
ForgeFPGA Dev. Board R1.1 User Guide
[4]
ForgeFPGA Socket Adapter Quick Start Guide R1.0
Rev.1.0
May 31, 2022
Software, Software Download and User Guide, Renesas Electronics Corporation
User Manual
Page 1
© 2022 Renesas Electronics
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Summary of Contents for Renesas ForgeFPGA
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Page 1: Table Of Contents
User Manual ForgeFPGA Configuration Guide This document describes how to configure the ForgeFPGA core from three different configuration bitstream sources: External SPI/QSPI Flash, Internal OTP, MCU as a host. Contents Terms and Definitions ........................... 1 References ..............................1 Introduction ..............................2 General SPI Interface ............................. -
Page 2: Introduction
ForgeFPGA Configuration Guide 3. Introduction An internal Configuration Wrapper is used to configure the ForgeFPGA core. The configuration can be done from three different configuration bitstream sources: – External SPI/QSPI Flash – Internal OTP – MCU as a host The ForgeFPGA Designer Software is used to generate bitstreams. The schematic in... -
Page 3: Spi Modes With Clock Polarity And Clock Phase
ForgeFPGA Configuration Guide 3. MISO: Master-In Slave-Out (data output from slave). MISO is a data pin. This pin is used to transmit data from the slave to the master. Whenever the slave sends data, that data will be collected over the MISO pin by the master. -
Page 4: Development Board
RTL Synthesis : After creating your desired Verilog Code in the HDL Editor Window of the ForgeFPGA Workshop, the next step is to create a Netlist of your design. This can be done with the help of the built- in Synthesis tool that takes input design and produces a Netlist out of it. - Page 5 Also, the board can be used as an independent unit. The chip can be powered through the EXT PWR connector and signals can be read through the through-hole 12-pin connectors (Pmod connectors). Figure 5: ForgeFPGA Development Board Overview To configure the development board and read the desired output, connect the Development Board with the Socket Adapter through the PCIe connectors.
- Page 6 ForgeFPGA Configuration Guide Figure 6: Debugging Controls Panel Figure 7: ForgeFPGA Socket Adapter, Top View Rev.1.0 Page 6 May 31, 2022...
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Page 7: Otp Read/Write
ForgeFPGA Configuration Guide Figure 8: Assembled Equipment for Working with the Chip 6. OTP Read/Write The configuration for the FPGA is stored in the Configuration RAM. The Configuration RAM is a volatile memory that stores the FPGA design. The OTP memory loads the Configuration RAM. The SLG47910 contains three... - Page 8 ForgeFPGA Configuration Guide Figure 9. SLG47910 Block Diagram The loading of the data through different bitstream sources follow a particular flow and different values of the signal help in determining the mode of operation. The Figure 10 below showcases a part of that flow.
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Page 9: Writing The Otp Block
ForgeFPGA Configuration Guide Figure 10: Power Sequencing through Different Modes Writing the OTP Block The OTP is written using the SPI Slave interface. The OTP write starts with ramp up of the voltage signals VDDC to 1.1 V and VDDIO to 2.9 V which sets the NVM into write program mode. There is an otp_controller that sequences the internal signals to enable the OTP write. -
Page 10: Reading The Otp Block
ForgeFPGA Configuration Guide Table 3: OTP Write Packet Format (Incoming) Bits Byte 1 W/Rn (1) SP/AP (0) O1_A[15] O1_A[14] O1_A[13] Byte 2 O1_A[12] O1_A[11] O1_A[10] O1_A[8] O1_A[7] O1_A[6] O1_A[5] O1_A[4] Byte 3 O1_A[3] O1_A[2] O1_A[1] O1_A[0] O1_D[3] O1_D[2] O1_D[1] O1_D[0]... -
Page 11: Read Command Structure
ForgeFPGA Configuration Guide Figure 12. OTP Read Timing Read Command Structure Table 5: NVM OTP Read Command Packet Format Bits Byte 1 nRead (0) Byte 2 A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] Byte 3 A[10] A[4] A[3] A[2]... - Page 12 ForgeFPGA Configuration Guide GPIO5 SPI_SI (MISO) GPIO6 SPI_SO (MOSI) Figure 13. SPI Release from Deep Power Down Command After the 10 us is up, the SPI Master sends a Fast Read Command with 24-Address on the SPI_SO pin and receives the data on the SPI_SI port as shown (see Figure 14).
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Page 13: Mcu Programming (Slave Mode)
Figure 15. SPI MCU Mode Timing A 32-bit synchronization word will be inserted in the beginning of the bitstream by the ForgeFPGA Compiler. The SLG47910 will check this synchronization word to determine if the transfer is targeting this device. If the synchronization word does not match this device, then the configuration bitstream will be discarded. -
Page 14: Conclusion
ForgeFPGA Configuration Guide * During POSTAMBLE phase the CONFIG pin will strobe for 50ns. If the bitstream is invalid the CONFIG pin will strobe for 1.5us. If a load error occurred the Config pin will stay LOW. **SPI Frequency could be from kHz to MHz Conclusion The three configuration options, OTP, MCU and QSPI/SPI were reviewed. -
Page 15: Revision History
ForgeFPGA Configuration Guide 9. Revision History Revision Date Description 10-Mar-2022 Initial Version Rev.1.0 Page 15 May 31, 2022...
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