Data Transfer Control Registers (Dtcr) - Renesas F-ZTAT H8 Series Hardware Manual

In repeat mode, ETCRH functions as an 8-bit transfer counter and ETCRL holds the initial
transfer count. ETCRH is decremented by 1 each time one transfer is executed. When ETCRH
reaches H'00, the value in ETCRL is reloaded into ETCRH and the same operation is repeated.
The ETCRs are not initialized by a reset or in standby mode.
8.2.4

Data Transfer Control Registers (DTCR)

A data transfer control register (DTCR) is an 8-bit readable/writable register that controls the
operation of one DMAC channel.
Bit 7
DTE
Initial value 0
Read/Write R/W
Data transfer enable
Enables or disables
data transfer
Data transfer size
Selects byte or
word size
The DTCRs are initialized to H'00 by a reset and in standby mode.
Bit 7—Data Transfer Enable (DTE): Enables or disables data transfer on a channel. When the
DTE bit is set to 1, the channel waits for a transfer to be requested, and executes the transfer when
activated as specified by bits DTS2 to DTS0. When DTE is 0, the channel is disabled and does not
accept transfer requests. DTE is set to 1 by reading the register when DTE is 0, then writing 1.
Bit 7: DTE Description
0 Data transfer is disabled. In I/O mode or idle mode, DTE is cleared to 0 when
the specified number of transfers have been completed.
1 Data transfer is enabled
6 5
DTSZ DTID
0 0
R/W R/W
Data transfer
increment/decrement
Selects whether to
increment or decrement
the memory address
register
Repeat enable
Selects repeat
mode
4 3 2
RPE DTIE DTS2
0 0 0
R/W R/W R/W
Data transfer select
These bits select the data
transfer activation source
Data transfer interrupt enable
Enables or disables the CPU interrupt
at the end of the transfer
Rev. 3.00 Mar 21, 2006 page 195 of 814
Section 8 DMA Controller
1 0
DTS1 DTS0
0 0
R/W R/W
(Initial value)
REJ09B0302-0300