Renesas F-ZTAT H8 Series Hardware Manual page 206

Section 7 Refresh Controller
Contention between RTCNT Write and Increment: If an increment pulse occurs in the T
of an RTCNT write cycle, writing takes priority and RTCNT is not incremented. See figure 7.21.
φ
Address bus
Internal
write signal
RTCNT
input clock
RTCNT
Figure 7.21 Contention between RTCNT Write and Increment
Rev. 3.00 Mar 21, 2006 page 178 of 814
REJ09B0302-0300
RTCNT write cycle by CPU
T T
1 2
RTCNT address
N
Counter write data
T
3
M
state
3