Renesas F-ZTAT H8 Series Hardware Manual page 678

Section 21 Electrical Characteristics
φ
A to A
9 1
AS
CS (RAS)
3
HWR (UCAS),
LWR (LCAS)
RD (WE)
RFSH
Figure 21.11 DRAM Bus Timing (Refresh Cycle): Three-State Access
φ
CS (RAS)
3
HWR UCAS
( ),
LWR LCAS)
(
RFSH
Figure 21.12 DRAM Bus Timing (Self-Refresh Mode)
Rev. 3.00 Mar 21, 2006 page 650 of 814
REJ09B0302-0300
T T
1 2
t
ASD
t
CSR
t t
ASD RAD2
t
RAD2
t
CSR
— 2 CAS CAS Mode —
CAS CAS
t
CSR
t
CSR
— 2 CAS CAS Mode —
CAS CAS
T
3
t
SD
t
RAD3
t
SD
t
RAD3