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RTMCSR—Refresh Timer Control/Status Register
Bit
7
CMF
Initial value
0
Read/Write
R/(W)
Compare match flag
0 [Clearing condition]
1 [Setting condition]
Note:
Only 0 can be written, to clear the flag.
*
6
5
CMIE
CKS2
0
0
*
R/W
R/W
Clock select 2 to 0
Bit 5
CKS2
Compare match interrupt enable
0 The CMI interrupt requested by CMF is disabled
1 The CMI interrupt requested by CMF is enabled
Read CMF when CMF = 1, then write 0 in CMF
RTCNT = RTCOR
Appendix B Internal I/O Register
4
3
CKS1
CKS0
0
0
R/W
R/W
Bit 4
Bit 3
CKS1
CKS0
Counter Clock Source
0
0
0
Clock input is disabled
φ/2
1
φ/8
1
0
φ/32
1
φ/128
1
0
0
φ/512
1
φ/2048
1
0
φ/4096
1
Rev. 3.00 Mar 21, 2006 page 747 of 814
H'AD
Refresh controller
2
1
—
—
1
1
—
—
REJ09B0302-0300
0
—
1
—
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