Renesas F-ZTAT H8 Series Hardware Manual page 762

Appendix B Internal I/O Register
GRB3 H/L—General Register B3 H/L
Bit 15
Initial value 1
Read/Write R/W
BRA3 H/L—Buffer Register A3 H/L
Bit 15
1
Initial value
R/W
Read/Write
BRB3 H/L—Buffer Register B3 H/L
Bit 15
Initial value 1
Read/Write R/W
Rev. 3.00 Mar 21, 2006 page 734 of 814
REJ09B0302-0300
14 13 12 11 10
1 1 1 1
R/W R/W R/W R/W R/W
Output compare or input capture register (can be buffered)
14 13 12 11 10
1 1 1 1
R/W R/W R/W R/W R/W
Used in combination with GRA when buffer operation is selected
14 13 12 11 10
1 1 1 1
R/W R/W R/W R/W R/W
Used in combination with GRB when buffer operation is selected
9 8 7 6
1 1 1 1 1
R/W R/W R/W R/W
9 8 7 6
1 1 1 1 1
R/W R/W R/W R/W
9 8 7 6
1 1 1 1 1
R/W R/W R/W R/W
H'8A, H'8B
5 4 3 2
1 1 1 1
R/W R/W R/W R/W R/W
H'8C, H'8D
5 4 3 2
1 1 1 1
R/W R/W R/W R/W R/W
H'8E, H'8F
5 4 3 2
1 1 1 1
R/W R/W R/W R/W R/W
ITU3
1 0
1 1
R/W
ITU3
1 0
1 1
R/W
ITU3
1 0
1 1
R/W