Pwm Mode - Renesas F-ZTAT H8 Series Hardware Manual

Hide thumbs Also See for F-ZTAT H8 Series:

Table of Contents

Example of Synchronization: Figure 10.27 shows an example of synchronization. Channels 0, 1,

and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing

by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The

timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by

compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA

. For further information on PWM mode, see section 10.4.4, PWM Mode.

Value of TCNT0 to TCNT2

PWM Mode

In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin.

GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which

the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a

PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can

be selected in all channels (0 to 4).

Table 10.4 summarizes the PWM output pins and corresponding registers. If the same value is set

in GRA and GRB, the output does not change when compare match occurs.

Cleared by compare match with GRB0

Figure 10.27 Synchronization (Example)

Section 10 16-Bit Integrated Timer Unit (ITU)

Rev. 3.00 Mar 21, 2006 page 351 of 814

REJ09B0302-0300