Renesas F-ZTAT H8 Series Hardware Manual page 729

DTCR0A—Data Transfer Control Register 0A (cont)
• Full address mode
Bit 7
DTE
Initial value 0
Read/Write R/W
Source address increment/decrement (bit 5)
Source address increment/decrement enable (bit 4)
Bit 5 Bit 4
SAID SAIDE
0 0
1
1 0
1
Data transfer size
0 Byte-size transfer
1 Word-size transfer
Data transfer enable
0 Data transfer is disabled
1 Data transfer is enabled
6 5
DTSZ SAID
0 0
R/W R/W
Increment/Decrement Enable
MARA is held fixed
Incremented: If DTSZ = 0, MARA is incremented by 1 after each transfer
If DTSZ = 1, MARA is incremented by 2 after each transfer
MARA is held fixed
Decremented: If DTSZ = 0, MARA is decremented by 1 after each transfer
If DTSZ = 1, MARA is decremented by 2 after each transfer
Appendix B Internal I/O Register
H'27
4 3
SAIDE DTIE DTS2A
0 0
R/W R/W R/W
Data transfer select 0A
Data transfer select 2A and 1A
Set both bits to 1
Data transfer interrupt enable
0 Interrupt request by DTE bit is disabled
1 Interrupt request by DTE bit is enabled
Rev. 3.00 Mar 21, 2006 page 701 of 814
DMAC0
2 1 0
DTS1A DTS0A
0 0 0
R/W R/W
0 Normal mode
1 Block transfer mode
REJ09B0302-0300