Renesas F-ZTAT H8 Series Hardware Manual page 64

Section 2 CPU
Table 2.5 Logic Operation Instructions
Size *
Instruction
AND B/W/L
OR B/W/L
XOR B/W/L
NOT B/W/L
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6 Shift Instructions
Size *
Instruction
SHAL, B/W/L
SHAR
SHLL, B/W/L
SHLR
ROTL, B/W/L
ROTR
ROTXL, B/W/L
ROTXR
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
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REJ09B0302-0300
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
¬ Rd → Rd
Takes the one's complement of general register contents.
Function
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
Rd (shift) → Rd
Performs a logical shift on general register contents.
Rd (rotate) → Rd
Rotates general register contents.
Rd (rotate) → Rd
Rotates general register contents through the carry bit.