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Item
21.2.2 AC Characteristics
Table 21.7 Timing of On-
Chip Supporting Modules
21.2.3 A/D Conversion
Characteristics
Table 21.8 A/D Converter
Characteristics
21.2.4 D/A Conversion
Characteristics
Table 21.9 D/A Converter
Characteristics
21.2.5 Flash Memory
Characteristics
Table 21.10 Flash
Memory Characteristics
A.1 Instruction List
Table A.1 Instruction Set
2. Arithmetic instructions
Rev. 3.00 Mar 21, 2006 page xii of xxviii
Page
Revisions (See Manual for Details)
639
Condition A and Condition B deleted
Table and notes amended
Item
DREQ setup time
DMAC
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
640
Condition A and Condition B deleted
Table and notes amended
Item
Conversion time
Notes: 1 The value is for φ ≤ 13 MHz.
2 The value is for φ > 13 MHz.
641
Condition A and Condition B deleted
642, 643
Condition A and Condition B deleted
Table and notes amended
Item
Reprogramming count
Data retention period
Notes: 6.
Minimum cycle value which guarantees all characteristics after reprogramming.
(Reprogram cycles from 1 to minimum value are guaranteed.)
7.
Reference characteristics at 25˚C. (This is a indication that reprogram operation can
normally function up to this figure.)
8.
Data retention characteristics when reprogaram performed correctly within
specification value including minimum data retention period.
663
Table amended
Mnemonic
DAA Rd
Symbol
Min
t
20
DRQS
t
10
DRQH
t
—
TED1
t
—
TED2
t
—
TOCD
t
40
TICS
t
40
TCKS
Single edge
t
1.5
TCKWH
Both edges
t
2.5
TCKWL
Min
5.36
Symbol Min
100 *
N
WEC
10 *
8
T
DRP
Addressing Mode and
Instruction Length (bytes)
Operation
B
Rd8 decimal adjust
2
→ Rd8
Conditions
Test
Max
Unit
Conditions
—
ns
Figure 21.16
—
50
Figure 21.24,
Figure 21.25
50
50
ns
Figure 21.20
—
—
Figure 21.21
—
t
cyc
—
t
scyc
Conditions
Typ
Max
—
—
Conditions
Typ
Max
Unit
Notes
6
10.000 *
7
—
Times
—
—
Years
No. of
States
Condition Code
I
H
N
Z
V
C
—
*
*1
2
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