Table of Contents
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Section 1 Overview
Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
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•
•
Memory
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•
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Interrupt
controller
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Rev. 3.00 Mar 21, 2006 page 2 of 814
REJ09B0302-0300
General-register machine
Sixteen 16-bit general registers
(also usable as + eight 16-bit registers or eight 32-bit registers)
High-speed operation
Maximum clock rate: 25 MHz
Add/subtract: 80 ns
Multiply/divide: 560 ns
16-Mbyte address space
Instruction features
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16
bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16
bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
Flash memory: 512 kbytes
RAM: 8 kbytes
Seven external interrupt pins: NMI, IRQ
30 internal interrupts
Three selectable interrupt priority levels
to IRQ
0
5
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