Renesas F-ZTAT H8 Series Hardware Manual page 640

Section 19 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency (φ)
when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, and figure
19.6 shows the external clock input timing. Figure 19.7 shows the external clock output
stabilization delay timing.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 19.3 Clock Timing
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock low pulse width
Clock high pulse width
External clock output
settling delay time
Note: * t includes 10 t
DEXT
EXTAL
Rev. 3.00 Mar 21, 2006 page 612 of 814
REJ09B0302-0300
DEXT
V
CC
V
CC
Symbol Min
t 15
EXL
t 15
EXH
t —
EXr
t —
EXf
t 0.4
CL
80
t 0.4
CH
80
*
t 500
DEXT
of RES pulse width (t
cyc
t
EXH
t
EXr
Figure 19.6 External Clock Input Timing
) has passed after the clock input. The system
, while the clock output is unstable.
DEXT
= 5.0 V ± 10%
= 3.0V to 3.6V
Max Unit
— ns
— ns
5 ns
5 ns
0.6 t
— ns
0.6 t
— ns
— µs
).
RESW
t
EXL
× 0.7
V
CC
0.3 V
t
EXf
Test Conditions
Figure 19.6
φ ≥ 5 MHz
Figure 21.4
cyc
φ < 5 MHz
φ ≥ 5 MHz
cyc
φ < 5 MHz
Figure 19.7
× 0.5
V
CC