Renesas F-ZTAT H8 Series Hardware Manual page 833

State: Figure D.2 is a timing diagram for the case in which RES goes low during the
Reset in T
2
state of an external memory access cycle. As soon as RES goes low, all ports are initialized to
T
2
the input state. AS, RD, HWR, and LWR go high, and the data bus goes to the high-impedance
state. The address bus is initialized to the low output level 0.5 state after the low level of RES is
sampled. The same timing applies when a reset occurs during a wait state (T
φ
RES
Internal
reset signal
Address bus
CS
0
CS to CS
7 1
AS
RD (read access)
HWR, LWR
(write access)
Data bus
(write access)
I/O port
Figure D.2 Reset during Memory Access (Reset during T
Access to external address
T T
1 2
Rev. 3.00 Mar 21, 2006 page 805 of 814
Appendix D Pin States
).
W
T
3
H'000000
High impedance
High impedance
High impedance
State)
2
REJ09B0302-0300