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Section 10 16-Bit Integrated Timer Unit (ITU)
Clearing Procedure for Complementary PWM Mode: Figure 10.34 shows the steps to clear
complementary PWM mode.
Complementary PWM mode
Clear complementary PWM mode
Stop counter operation
Normal operating mode
Figure 10.34 Clearing Procedure for Complementary PWM Mode
Rev. 3.00 Mar 21, 2006 page 360 of 814
REJ09B0302-0300
1. Clear the CMD1 bit of TFCR to 0 to
set channels 3 and 4 to normal
operating mode.
2. After setting channels 3 and 4 to
normal operating mode, wait at least
1
one counter clock period, then clear
bits STR3 and STR4 of TSTR to 0 to
stop counter operation of TCNT3 and
TCNT4.
2
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