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Block Diagram of Channels 0 and 1: ITU channels 0 and 1 are functionally identical. Both have
the structure shown in figure 10.2.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
Legend:
TCNT:
Timer counter (16 bits)
GRA, GRB:
General registers A and B (input capture/output compare registers) (16 bits
TCR:
Timer control register (8 bits)
TIOR:
Timer I/O control register (8 bits)
TIER:
Timer interrupt enable register (8 bits)
TSR:
Timer status register (8 bits)
Figure 10.2 Block Diagram of Channels 0 and 1 (for Channel 0)
Section 10 16-Bit Integrated Timer Unit (ITU)
Clock selector
Comparator
Module data bus
Control logic
Rev. 3.00 Mar 21, 2006 page 307 of 814
TIOCA
0
TIOCB
0
IMIA0
IMIB0
OVI0
×
2)
REJ09B0302-0300
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