Renesas F-ZTAT H8 Series Hardware Manual page 224

Section 8 DMA Controller
If DTIE is set to 1, a CPU interrupt is requested when DTE is cleared to 0.
Bit 6—Data Transfer Size (DTSZ): Selects the data size of each transfer.
Bit 6: DTSZ Description
0 Byte-size transfer
1 Word-size transfer
Bit 5—Data Transfer Increment/Decrement (DTID): Selects whether to increment or
decrement the memory address register (MAR) after a data transfer in I/O mode or repeat mode.
Bit 5: DTID Description
0 MAR is incremented after each data transfer
•
•
1 MAR is decremented after each data transfer
•
•
MAR is not incremented or decremented in idle mode.
Bit 4—Repeat Enable (RPE): Selects whether to transfer data in I/O mode, idle mode, or repeat
mode.
Bit 4: RPE Bit 3: DTIE
0 0
1
1 0
1
Operations in these modes are described in sections 8.4.2, I/O Mode, 8.4.3, Idle Mode, and 8.4.4,
Repeat Mode.
Bit 3—Data Transfer Interrupt Enable (DTIE): Enables or disables the CPU interrupt (DEND)
requested when the DTE bit is cleared to 0.
Bit 3: DTIE Description
0 The DEND interrupt requested by DTE is disabled
1 The DEND interrupt requested by DTE is enabled
Rev. 3.00 Mar 21, 2006 page 196 of 814
REJ09B0302-0300
If DTSZ = 0, MAR is incremented by 1 after each transfer
If DTSZ = 1, MAR is incremented by 2 after each transfer
If DTSZ = 0, MAR is decremented by 1 after each transfer
If DTSZ = 1, MAR is decremented by 2 after each transfer
Description
I/O mode
Repeat mode
Idle mode
(Initial value)
(Initial value)
(Initial value)