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9.3.2
Register Configuration
Table 9.3 summarizes the registers of port 2.
Table 9.3
Port 2 Registers
Address *
Name
H'FFC1
Port 2 data direction
register
H'FFC3
Port 2 data register
H'FFD8
Port 2 input pull-up MOS
control register
Note: * Lower 16 bits of the address.
Port 2 Data Direction Register (P2DDR)
P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2.
Bit
P2 DDR
7
Initial value
Modes
1 to 4
Read/Write
Initial value
Modes
5 to 7
Read/Write
• Modes 1 to 4 (Expanded Modes with On-Chip ROM Disabled)
P2DDR values are fixed at 1 and cannot be modified. Port 2 functions as an address bus.
• Modes 5 and 6 (Expanded Modes with On-Chip ROM Enabled)
Following a reset, port 2 is an input port. A pin in port 2 becomes an address output pin if the
corresponding P2DDR bit is set to 1, and a generic input port if this bit is cleared to 0.
• Mode 7 (Single-Chip Mode)
Port 2 functions as an input/output port. A pin in port 2 becomes an output port if the
corresponding P2DDR bit is set to 1, and an input port if this bit is cleared to 0.
Abbreviation
P2DDR
P2DR
P2PCR
7
6
5
P2 DDR
P2 DDR
6
5
1
1
1
—
—
—
0
0
0
W
W
W
R/W
W
R/W
R/W
4
3
P2 DDR
P2 DDR
4
3
1
1
—
—
0
0
W
W
Port 2 data direction 7 to 0
These bits select input or
output for port 2 pins
Rev. 3.00 Mar 21, 2006 page 253 of 814
Section 9 I/O Ports
Initial Value
Modes 1 to 4
Modes 5 to 7
H'FF
H'00
H'00
H'00
H'00
H'00
2
1
P2 DDR
P2 DDR
2
1
1
1
—
—
0
0
W
W
REJ09B0302-0300
0
P2 DDR
0
1
—
0
W
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