Usage Notes - Renesas F-ZTAT H8 Series Hardware Manual

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Usage Notes

When using the SCI as a smart card interface, note the following points.

Receive Data Sampling Timing in Smart Card Mode and Receive Margin: In smart card mode

the SCI operates on a base clock with 372 times the bit rate frequency. In receiving, the SCI

synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive

data is latched at the rising edge of the 186th base clock pulse. See figure 14.10.

Receive data

Synchronization

sampling timing

Data sampling

Figure 14.10 Receive Data Sampling Timing in Smart Card Mode

The receive margin can therefore be expressed as follows.

Receive margin in smart card mode:

M: Receive margin (%)

N: Ratio of clock frequency to bit rate (N = 372)

D: Clock duty cycle (D = 0 to 1.0)

L: Frame length (L = 10)

F: Absolute deviation of clock frequency

– (L – 0.5) F –

(1 + F) × 100%

Rev. 3.00 Mar 21, 2006 page 517 of 814

Section 14 Smart Card Interface

REJ09B0302-0300