Block Diagram; Register Configuration - Renesas F-ZTAT H8 Series Hardware Manual

Section 12 Watchdog Timer
12.1.2

Block Diagram

Figure 12.1 shows a block diagram of the WDT.
Interrupt signal
(interval timer)
Reset (internal)
Legend:
TCNT: Timer counter
TCSR: Timer control/status register
RSTCSR: Reset control/status register
12.1.3

Register Configuration

Table 12.1 summarizes the WDT registers.
Table 12.1 WDT Registers
Address * 1
Write *
2
Read
H'FFA8 H'FFA8
H'FFA9
H'FFAA H'FFAB
Notes: 1. Lower 16 bits of the address.
2. Write word data starting at this address.
3. Only 0 can be written in bit 7, to clear the flag.
Rev. 3.00 Mar 21, 2006 page 424 of 814
REJ09B0302-0300
Overflow
Interrupt
control
RSTCSR
Reset control
Figure 12.1 WDT Block Diagram
Name
Timer control/status register
Timer counter
Reset control/status register
TCNT
TCSR
Clock
Clock
selector
Abbre-
viation
TCSR
TCNT
RSTCSR
Internal
data bus
Read/
write
control
Internal clock sources
φ/2
φ/32
φ/64
φ/128
φ/256
φ/512
φ/2048
φ/4096
Initial
R/W
Value
R/(W) * 3
H'18
R/W H'00
R/(W) *
3
H'3F