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Section 10 16-Bit Integrated Timer Unit (ITU)
10.1.2
Block Diagrams
ITU Block Diagram (Overall): Figure 10.1 is a block diagram of the ITU.
TCLKA to TCLKD
φ, φ/2, φ/4, φ/8
TOCXA
, TOCXB
4
4
TIOCA
to TIOCA
0
4
TIOCB
to TIOCB
0
4
Legend:
TOER:
Timer output master enable register (8 bits)
TOCR:
Timer output control register (8 bits)
TSTR:
Timer start register (8 bits)
TSNC:
Timer synchro register (8 bits)
TMDR:
Timer mode register (8 bits)
TFCR:
Timer function control register (8 bits)
Rev. 3.00 Mar 21, 2006 page 306 of 814
REJ09B0302-0300
Clock selector
Control logic
Module data bus
Figure 10.1 ITU Block Diagram (Overall)
IMIA0 to IMIA4
IMIB0 to IMIB4
OVI0 to OVI4
TOER
TOCR
TSTR
TSNC
TMDR
TFCR
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