Pin Configuration; Register Configuration - Renesas F-ZTAT H8 Series Hardware Manual

Section 18 ROM
18.3

Pin Configuration

The flash memory is controlled by means of the pins shown in table 18.1.
Table 18.1 Pin Configuration
Pin Name
Reset
Flash write enable
Mode 2
Mode 1
Mode 0
Transmit data
Receive data
18.4

Register Configuration

The registers *
1
used to control the on-chip flash memory when enabled are shown in table 18.2.
Table 18.2 Register Configuration
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM control register
Notes: 1. Access is prohibited to lower 16 address bits H'FF44 to H'FF46 and H'FF48 to H'FF4F.
2. Lower 16 bits of the address.
3. If the chip is in a mode in which the on-chip flash memory is disabled, a read will return
H'00 and writes are invalid. Writes are also invalid when the FWE bit in FLMCR1 is not
set to 1.
4. When a high level is input to the FWE pin, the initial value is H'80.
5. When a low level is input to the FWE pin, or if a high level is input and the SWE1 bit in
FLMCR1 or SWE2 bit in FLMCR2 is not set, these registers are initialized to H'00.
6. FLMCR1, FLMCR2, EBR1, and EBR2, and RAMCR are 8-bit registers.
Byte access must be used on these registers (do not use word or longword access).
Rev. 3.00 Mar 21, 2006 page 564 of 814
REJ09B0302-0300
Abbreviation I/O
RES
Input
FWE Input
MD2 Input
MD1 Input
MD0 Input
TxD1 Output
RxD1 Input
Abbreviation
FLMCR1 *
FLMCR2 *
6
EBR1 *
6
EBR2 *
6
RAMCR *
Function
Reset
Flash program/erase protection by hardware
Sets LSI operating mode
Sets LSI operating mode
Sets LSI operating mode
Serial transmit data output
Serial receive data input
R/W Initial Value
6 R/W * 3
H'00 *
6 R/W * 3
H'00
R/W * 3
H'00 *
3
R/W * H'00 *
R/W H'F0
Address * 2
4
H'FF40
H'FF41
5
H'FF42
5
H'FF43
H'FF47