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Section 6 Bus Controller
H8/3052BF
CS
CS
CS
WAIT
HWR
LWR
A
to A
23
D
to D
15
D to D
7
Figure 6.18 Interconnections with Memory (Example)
Rev. 3.00 Mar 21, 2006 page 138 of 814
REJ09B0302-0300
0
1
2
RD
0
8
0
EPROM
A
to A
19
1
A
to A
18
0
I/O
to I/O
15
I/O to I/O
7
0
CE
OE
SRAM1 (even addresses)
A
to A
15
1
A
to A
14
0
I/O to I/O
7
CS
OE
WE
SRAM2 (odd addresses)
A
to A
15
1
A
to A
14
0
I/O to I/O
7
0
CS
OE
WE
SRAM3
A
to A
14
0
A
to A
14
0
I/O to I/O
7
0
CS
OE
WE
8
0
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