Renesas F-ZTAT H8 Series Hardware Manual page 21

10.2 Register Descriptions ........................................................................................................ 315
10.2.1 Timer Start Register (TSTR)................................................................................ 315
10.2.2 Timer Synchro Register (TSNC) ......................................................................... 316
10.2.3 Timer Mode Register (TMDR) ............................................................................ 318
10.2.4 Timer Function Control Register (TFCR)............................................................ 321
10.2.5 Timer Output Master Enable Register (TOER) ................................................... 323
10.2.6 Timer Output Control Register (TOCR) .............................................................. 325
10.2.7 Timer Counters (TCNT) ...................................................................................... 326
10.2.8 General Registers (GRA, GRB)........................................................................... 327
10.2.9 Buffer Registers (BRA, BRB) ............................................................................. 328
10.2.10 Timer Control Registers (TCR) ........................................................................... 329
10.2.11 Timer I/O Control Register (TIOR) ..................................................................... 331
10.2.12 Timer Status Register (TSR)................................................................................ 333
10.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 335
10.3 CPU Interface.................................................................................................................... 337
10.3.1 16-Bit Accessible Registers ................................................................................. 337
10.3.2 8-Bit Accessible Registers ................................................................................... 339
10.4 Operation........................................................................................................................... 340
10.4.1 Overview.............................................................................................................. 340
10.4.2 Basic Functions.................................................................................................... 341
10.4.3 Synchronization ................................................................................................... 350
10.4.4 PWM Mode.......................................................................................................... 351
10.4.5 Reset-Synchronized PWM Mode......................................................................... 355
10.4.6 Complementary PWM Mode ............................................................................... 358
10.4.7 Phase Counting Mode .......................................................................................... 367
10.4.8 Buffering.............................................................................................................. 369
10.4.9 ITU Output Timing .............................................................................................. 376
10.5 Interrupts ........................................................................................................................... 378
10.5.1 Setting of Status Flags.......................................................................................... 378
10.5.2 Clearing of Status Flags ....................................................................................... 380
10.5.3 Interrupt Sources and DMA Controller Activation.............................................. 381
10.6 Usage Notes ...................................................................................................................... 382
Section 11 Programmable Timing Pattern Controller
11.1 Overview........................................................................................................................... 397
11.1.1 Features................................................................................................................ 397
11.1.2 Block Diagram ..................................................................................................... 398
11.1.3 Pin Configuration................................................................................................. 399
11.1.4 Register Configuration......................................................................................... 400
11.2 Register Descriptions ........................................................................................................ 401
............................................... 397
Rev. 3.00 Mar 21, 2006 page xxi of xxviii