Renesas F-ZTAT H8 Series Hardware Manual page 205

Contention between RTCNT Write and Counter Clear: If a counter clear signal occurs in the
T state of an RTCNT write cycle, clearing of the counter takes priority and the write is not
3
performed. See figure 7.20.
φ
Address bus
Internal
write signal
Counter
clear signal
RTCNT
Figure 7.20 Contention between RTCNT Write and Clear
RTCNT write cycle by CPU
T T
1 2
RTCNT address
N
Rev. 3.00 Mar 21, 2006 page 177 of 814
Section 7 Refresh Controller
T
3
H'00
REJ09B0302-0300