Renesas F-ZTAT H8 Series Hardware Manual page 634

Section 18 ROM
φ
t
OSC1
V
CC
FWE
MD to MD
2 0
RES
SWE1 (2) set
SWE1 (2) bit
Mode switching
Flash memory access disabled time
(x: Wait time after SWE1 (2) setting)
Flash memory reprogammable period
(Flash memory program execution and data read, other than verify, are disabled.)
Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES
input is necessary.
During this switching period (period during which a low level is input to the RES pin),the state of the address
dual port and bus control output signals (AS, RD, WR) changes.
Therefore, do not use these pins as output signals during this switching period.
2. When making a transition from the boot mode to another mode, the mode programming setup time t
to the RES clear timing is necessary.
3. See 21.2.5 Flash Memory Characteristics.
(Example: Boot mode → → → → User mode ↔
Rev. 3.00 Mar 21, 2006 page 606 of 814
REJ09B0302-0300
Programming
Wait
and erase
time: x
possible
Min 0 µs
t
t
MDS
t
MDS
t
RESW
SWE1 (2) clear
*1
Boot mode Mode
switching
*3
Figure 18.20 Mode Transition Timing
Programming
and
Wait erase Wait
time: x possible time: x
t
H
*2
MDS
User User program mode
*1
mode
↔ User program mode) ↔ ↔
Programming Programming
Wait
and erase and erase
time: x
possible possible
User User
mode program
mode
MDS
relative