Renesas F-ZTAT H8 Series Hardware Manual page 145

Bit 5—Address 21 Enable (A21E): Enables PA
Writing 0 in this bit enables A
cannot be modified and PA
Bit 5: A21E Description
0 PA
1 PA
Bits 4 to 1—Reserved: Read-only bits, always read as 1.
Bit 0—Bus Release Enable (BRLE): Enables or disables release of the bus to an external device.
Bit 0: BRLE Description
The bus cannot be released to an external device; BREQ and BACK can be
0
used as input/output pins
1 The bus can be released to an external device
address output from PA
21
has its ordinary input/output functions.
6
is the A address output pin
6 21
is the PA /TP /TIOCA
6 6 6
to be used as the A
6
. In modes other than 3, 4, and 6 this bit
6
input/output pin
2
Rev. 3.00 Mar 21, 2006 page 117 of 814
Section 6 Bus Controller
address output pin.
21
(Initial value)
(Initial value)
REJ09B0302-0300