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Table 21.7 Timing of On-Chip Supporting Modules
Conditions:
V
= 5.0 V ±10%, AV
CC
V
= AV
SS
Item
DREQ setup time
DMAC
DREQ hold time
TEND delay time 1
TEND delay time 2
ITU
Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock
pulse width
SCI
Input clock
cycle
Input clock rise time
Input clock fall time
Input clock pulse width
Transmit data delay time
Receive data setup time
(synchronous)
Receive data
hold time
(synchronous)
Ports and
Output data delay time
TPC
Input data setup time
Input data hold time
= 5.0 V ±10%, V
CC
= 0 V, φ = 2 MHz to 25 MHz, T
SS
Single edge
Both edges
Asynchronous
Synchronous
Clock input
Clock output
Section 21 Electrical Characteristics
= 4.5 V to AV
REF
= –20°C to +75°C
a
Conditions
Symbol
Min
Max
t
20
—
DRQS
t
10
—
DRQH
t
—
50
TED1
t
—
50
TED2
t
—
50
TOCD
t
40
—
TICS
t
40
—
TCKS
t
1.5
—
TCKWH
t
2.5
—
TCKWL
t
4
—
SCYC
t
6
—
SCYC
t
—
1.5
SCKr
t
—
1.5
SCKf
t
0.4
0.6
SCKW
t
—
100
TXD
t
100
—
RXS
t
100
—
RXH
t
0
—
RXH
t
—
50
PWD
t
50
—
PRS
t
50
—
PRH
Rev. 3.00 Mar 21, 2006 page 639 of 814
,
CC
Test
Unit
Conditions
ns
Figure 21.16
Figure 21.24,
Figure 21.25
ns
Figure 21.20
Figure 21.21
t
cyc
t
scyc
t
Figure 21.22
cyc
t
scyc
ns
Figure 21.23
ns
Figure 21.19
REJ09B0302-0300
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