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Section 18 ROM
Set pins to boot program mode
1
and execute reset-start
Host transfers data (H'00)
2
continuously at prescribed bit rate
This LSI measures low period
of H'00 data transmitted by host
3
This LSI calculates bit rate
and sets value in bit rate register
After bit rate adjustment, this LSI
4
transmits one byte of H'00 data to
host to indicate end of adjustment
Host confirms normal reception
of bit rate adjustment end
5
indication (H'00), and transmits
one byte of H'55 data
After receiving H'55, this LSI
sends H'AA and receives two bytes
6
of the byte count (N) of the program
transferred to the on-chip RAM
This LSI transfers the user
program to RAM
This LSI calculates the remaining
7
number of bytes to be sent (N = N – 1)
end byte count
After branching to the
RAM boot program area
(H'FFDF10 to H'FFE70F),
this LSI checks the data in
the flashmemory user area.
8
All data = H'FF?
After sending H'AA, this LSI
branches to the RAM area
9
(H'FFE710) and executes the user
program transferred to the RAM
Rev. 3.00 Mar 21, 2006 page 576 of 814
REJ09B0302-0300
Start
*1
*2
Transfer
No
N = 0?
Yes
No
Yes
Erase all blocks of flash
*3
memory
Figure 18.7 Boot Mode Execution Procedure
1. Set this LSI to the boot mode and reset starts the LSI.
2. Set the host to the prescribed bit rate (4800, 9600,
19200) and consecutively send H'00 data in 8-bit data,
1 stop bit format.
3. This LSI repeatedly measures the RXD1 pin Low
period and calculates the asynchronous
communication bit rate at which the host performs
transfer.
4. At the end of SCI bit rate adjustment, this LSI sends
one byte of H'00 data to signal the end of adjustment.
5. Check if the host normally received the one byte bit
rate adjustment end signal sent from this LSI and sent
one byte of H'55 data.
6. After H'55 is sent, the host receives H'AA and sends
the byte count of the user program that is transferred to
this LSI. Send the 2-byte count in upper byte and lower
byte order. Then sequentially send the program set by
the user. This LSI sequentially sends (echo back) each
byte of the received byte count and user program to the
host as verification data.
7. This LSI sequentially writes the received user program
to the on-chip RAM area (H'FFE710 to H'FFFF0F).
8. Before executing the transferred user program, this LSI
checks if data was written to flash memory after control
branched to the RAM boot program area (H'FFDF10). If
data was already written to flash memory, all the blocks
are erased.
9. After sending H'AA, this LSI branches to the on-chip
RAM area (H'FFE710) and executes the user program
written to that area.
Notes: 1. The RAM area that can be used by the user is
6 kbyte. Set the transfer byte count to within 6
kbyte. Always send the 2-byte transfer byte
count in upper byte and lower byte order.
Transfer byte count example: For 256 bytes
(H'0100), upper byte H'01, lower byte H'00.
2. Set the part that controls the user program
flash memory at the program according to the
flash memory programming/erase algorithms
described later.
3. When a memory cell malfunctions and cannot
be erased, this LSI sends one H'FF byte as an
erase error and stops the erase operation and
subsequent operations.
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