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9.11.2
Register Configuration
Table 9.18 summarizes the registers of port A.
Table 9.18 Port A Registers
Address *
Name
H'FFD1
Port A data direction
register
H'FFD3
Port A data register
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that can select input or output for each pin in port A. When
pins are used for TPC output, the corresponding PADDR bits must also be set.
Bit
PA DDR
Modes
Initial value
3, 4,
and 6
Read/Write
Modes
Initial value
1, 2, 5,
Read/Write
and 7
A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input
pin if this bit is cleared to 0. In modes 3, 4, and 6, PA
address output pin.
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3, 4, and 6. In software
standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin
maintains its output state in software standby mode.
Abbreviation
PADDR
PADR
7
6
5
PA DDR
PA DDR
7
6
5
1
0
0
—
W
W
0
0
0
W
W
W
R/W
W
R/W
4
3
PA DDR
PA DDR
4
3
0
0
W
W
0
0
W
W
Port A data direction 7 to 0
These bits select input or output for port A pins
DDR is fixed at 1 and PA
7
Rev. 3.00 Mar 21, 2006 page 283 of 814
Section 9 I/O Ports
Initial Value
Modes
Modes
1, 2, 5 and 7
3, 4, and 6
H'00
H'80
H'00
H'00
2
1
PA DDR
PA DDR
2
1
0
0
W
W
0
0
W
W
functions as an
7
REJ09B0302-0300
0
PA DDR
0
0
W
0
W
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