Pin Configuration; Register Configuration - Renesas F-ZTAT H8 Series Hardware Manual

Section 7 Refresh Controller
7.1.3

Pin Configuration

Table 7.1 summarizes the refresh controller's input/output pins.
Table 7.1 Refresh Controller Pins
Pin Name
RFSH
Refresh
HWR
Upper write/upper column
address strobe
LWR
Lower write/lower column
address strobe
RD
Column address strobe/
write enable
CS
Row address strobe
3
7.1.4

Register Configuration

Table 7.2 summarizes the refresh controller's registers.
Table 7.2 Refresh Controller Registers
Address *
Name
H'FFAC Refresh control register
H'FFAD Refresh timer control/status register
H'FFAE Refresh timer counter
H'FFAF Refresh time constant register
Note: * Lower 16 bits of the address.
Rev. 3.00 Mar 21, 2006 page 148 of 814
REJ09B0302-0300
Signal
Abbr.
RFSH
UW/UCAS
LW/LCAS
CAS/WE
RAS
I/O Function
Output Goes low during refresh cycles;
used to refresh DRAM and PSRAM
Connects to the UW pin of 2WE
Output
DRAM or UCAS pin of 2CAS DRAM
Connects to the LW pin of 2WE
Output
DRAM or LCAS pin of 2CAS DRAM
Connects to the CAS pin of 2WE
Output
DRAM or WE pin of 2CAS DRAM
Connects to the RAS pin of DRAM
Output
Abbreviation
RFSHCR
RTMCSR
RTCNT
RTCOR
R/W Initial Value
R/W H'02
R/W H'07
R/W H'00
R/W H'FF