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Section 8 DMA Controller
Figure 8.18 shows the timing when the DMAC is activated by the falling edge of DREQ in block
transfer mode.
T
1
φ
DREQ
Address
bus
RD
HWR
LWR
,
TEND
Figure 8.18 Timing of DMAC Activation by Falling Edge of DREQ
Rev. 3.00 Mar 21, 2006 page 232 of 814
REJ09B0302-0300
DMAC cycle
T
T
T
T
T
2
1
2
1
2
End of 1 block transfer
CPU cycle
T
T
T
T
T
1
2
1
2
Next sampling
Minimum 4 states
DREQ in Block Transfer Mode
DREQ
DREQ
DMAC cycle
T
T
T
T
1
2
d
1
2
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