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Section 14 Smart Card Interface
(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
In case of normal transmission: TEND flag is set
In case of transmit error:
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14.5 Relation between Transmit Operation and Internal Registers
I/O data
DS
TXI
(TEND interrupt)
Rev. 3.00 Mar 21, 2006 page 512 of 814
REJ09B0302-0300
TDR
(shift register)
Data 1
Data 1
Data 1
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Da
Db
Dc
Dd
De
12.5 etu
11.0 etu
Figure 14.6 TEND Flag Occurrence Timing
TSR
Data 1
; Data remains in TDR
Data 1
Df
Dg
Dh
Dp
I/O signal line output
DE
Guard
GM = 0
GM = 1
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