Renesas F-ZTAT H8 Series Hardware Manual page 358

Section 10 16-Bit Integrated Timer Unit (ITU)
Bits 6 and 5—Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared.
Bit 6: CCLR1 Bit 5: CCLR0
0 0
1
1 0
1
Notes: 1. TCNT is cleared by compare match when the general register functions as an output
compare register, and by input capture when the general register functions as an input
capture register.
2. Selected in TSNC.
Bits 4 and 3—Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges
when an external clock source is used.
Bit 4: CKEG1 Bit 3: CKEG0
0 0
1
1 —
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock
source.
Bit 2: TPSC2 Bit 1: TPSC1
0 0
1
1 0
1
Rev. 3.00 Mar 21, 2006 page 330 of 814
REJ09B0302-0300
Description
TCNT is not cleared
TCNT is cleared by GRA compare match or input
capture * 1
TCNT is cleared by GRB compare match or input
capture *
1
Synchronous clear: TCNT is cleared in synchronization
with other synchronized timers *
Description
Count rising edges
Count falling edges
Count both edges
Bit 0: TPSC0 Description
Internal clock: φ
0
Internal clock: φ/2
1
Internal clock: φ/4
0
Internal clock: φ/8
1
0 External clock A: TCLKA input
1 External clock B: TCLKB input
0 External clock C: TCLKC input
1 External clock D: TCLKD input
(Initial value)
2
(Initial value)
(Initial value)