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Feature
Description
Bus controller
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Refresh
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controller
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DMA controller
(DMAC)
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Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of four wait modes
Bus arbitration function
DRAM refresh
Directly connectable to 16-bit-wide DRAM
CAS-before-RAS refresh
Self-refresh mode selectable
Pseudo-static RAM refresh
Self-refresh mode selectable
Usable as an interval timer
Short address mode
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, transmit-data-empty and receive-data-full interrupts from
SCI channel 0, or external requests
Full address mode
Maximum two channels available
Selection of normal mode or block transfer mode
Can be activated by compare match/input capture A interrupts from ITU
channels 0 to 3, external requests, or auto-request
Section 1 Overview
Rev. 3.00 Mar 21, 2006 page 3 of 814
REJ09B0302-0300
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