Nmi Input Disable Conditions - Renesas F-ZTAT H8 Series Hardware Manual

Figure 18.14 shows the flash memory state transition diagram.
RD VF PR ER FLER = 0
P = 1 or
P = 0 and
E = 1
E = 0
Program mode
Erase mode
RD VF PR ER FLER = 0
Error
occurrence
Error protection mode
RD VF PR ER FLER = 1
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
Figure 18.14 Flash Memory State Transitions (Modes 5, 6, and 7
(On-Chip ROM Enabled), High Level Applied to FWE Pin)
18.8.4

NMI Input Disable Conditions

While flash memory is being programed/erased and the boot program is executing in the boot
mode (however, period up to branching to on-chip RAM area) *
the programming/erasing operations have priority.
Memory read
verify mode
Reset or hardware standby
Software standby mode
Software standby
mode release
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
INIT: Register initialization state
Reset or standby
(hardware protection)
RD VF PR ER INIT FLER = 0
Reset or hardware
standby
Error protection mode
(software standby)
RD VF PR ER INIT FLER = 1
1
, NMI input is disabled because
Rev. 3.00 Mar 21, 2006 page 595 of 814
Section 18 ROM
REJ09B0302-0300