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• Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected by settings in
TIOR. Figure 10.25 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system
clocks for capture of both edges.
φ
Input-capture input
Internal input
capture signal
TCNT
GRA, GRB
Figure 10.25 Input Capture Signal Timing
Section 10 16-Bit Integrated Timer Unit (ITU)
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Rev. 3.00 Mar 21, 2006 page 349 of 814
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REJ09B0302-0300
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