Renesas F-ZTAT H8 Series Hardware Manual page 350

Section 10 16-Bit Integrated Timer Unit (ITU)
Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer
counter or counters that will be used in these modes.
When these bits select complementary PWM mode or reset-synchronized PWM mode, they take
precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of
timer sync bits SYNC4 and SYNC3 in TSNC are valid in complementary PWM mode and reset-
synchronized PWM mode, however. When complementary PWM mode is selected, channels 3
and 4 must not be synchronized (do not set bits SYNC3 and SYNC4 both to 1 in TSNC).
Bit 3—Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or
whether GRB4 is buffered by BRB4.
Bit 3: BFB4 Description
0 GRB4 operates normally
1 GRB4 is buffered by BRB4
Bit 2—Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or
whether GRA4 is buffered by BRA4.
Bit 2: BFA4 Description
0 GRA4 operates normally
1 GRA4 is buffered by BRA4
Bit 1—Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or
whether GRB3 is buffered by BRB3.
Bit 1: BFB3 Description
0 GRB3 operates normally
1 GRB3 is buffered by BRB3
Bit 0—Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or
whether GRA3 is buffered by BRA3.
Bit 0: BFA3 Description
0 GRA3 operates normally
1 GRA3 is buffered by BRA3
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