Renesas F-ZTAT H8 Series Hardware Manual page 187

Address Multiplexing: Address multiplexing depends on the setting of the M9/M8 bit in
RFSHCR, as described in table 7.5. Figure 7.4 shows the address output timing. Address output is
multiplexed only in area 3.
Table 7.5 Address Multiplexing
Address Pins
Address signals during row
address output
Address signals M9/M8 = 0
during column
address output
M9/M8 = 1
φ
A to A , A
23
Address
bus
A to A
8
φ
A to A , A
23
Address
bus
A to A
9
Figure 7.4 Multiplexed Address Output (Example without Wait States)
A to
23
A A
10 9
A to A
23 9
A
10
A to A
23 9
A
10
A to A
23 18
A
10
T
1
9 0
A to A
8
1
Row address
a. M9/
T
1
10 0
A to A
9
1
Row address
b. M9/
A A A A
8 7 6 5
A A A A
8 7 6 5
A A A A
9 16 15 14
A A A A
17 16 15 14
T
2
A to A , A
23 9 0
A
1
Column address
M8
= 0
T
2
A to A , A
23 10 0
A
1
Column address
M8
= 1
Rev. 3.00 Mar 21, 2006 page 159 of 814
Section 7 Refresh Controller
A A A A
4 3 2
A A A A
4 3 2
A A A A
13 12 11
A A A A
13 12 11
T
3
to A
16 9
T
3
to A
18 10
REJ09B0302-0300
A
1 0
A
1 0
A
10 0
A
10 0