Table of Contents
Advertisement
Refresh Cycle Priority Order: When there are simultaneous bus requests, the priority order is:
(High)
External bus master > refresh controller > DMA controller > CPU
For details see section 6.3.7, Bus Arbiter Operation.
Wait State Insertion: When bit AST3 is set to 1 in ASTCR, the wait state controller (WSC) can
insert wait states into bus cycles and refresh cycles. For details see section 6.3.5, Wait Modes.
Self-Refresh Mode: Some pseudo-static RAM devices have a self-refresh function. After the
SRFMD bit is set to 1 in RFSHCR, when a transition to software standby mode occurs, the
H8/3052BF' CS
output goes high and its RFSH output goes low so that the pseudo-static RAM
3
self-refresh function can be used. On exit from software standby mode, the RFSH output goes
high.
Table 7.8 shows the pin states in software standby mode. Figure 7.16 shows the signal output
timing.
Table 7.8
Pin States in Software Standby Mode (PSRAME = 1, DRAME = 0)
Signal
CS
3
RD
HWR
LWR
RFSH
SRFMD = 0
High
High-impedance
High-impedance
High-impedance
High
Software Standby Mode
SRFMD = 1 (Self-Refresh Mode)
High
High-impedance
High-impedance
High-impedance
Low
Rev. 3.00 Mar 21, 2006 page 173 of 814
Section 7 Refresh Controller
(Low)
REJ09B0302-0300
Advertisement
Table of Contents
