Renesas F-ZTAT H8 Series Hardware Manual page 171

DDR Write Timing: Data written to a data direction register (DDR) to change a CS
CS
output to generic input, or vice versa, takes effect starting from the T
n
cycle. Figure 6.21 shows the timing when the CS
φ
Address
bus
CS
1
BRCR Write Timing: Data written to switch between A
output takes effect starting from the T
timing when a pin is changed from generic input to A
φ
Address
bus
A to A
23 21
1
T
1
High impedance
Figure 6.21 DDR Write Timing
state of the BRCR write cycle. Figure 6.22 shows the
3
T
1
High impedance
Figure 6.22 BRCR Write Timing
pin is changed from generic input to CS
T T
2
P8DDR address
, A , or A output and generic input or
23 22 21
, A , or A output.
23 22 21
T T
2
BRCR address
Rev. 3.00 Mar 21, 2006 page 143 of 814
Section 6 Bus Controller
pin from
n
state of the DDR write
3
output.
1
3
3
REJ09B0302-0300